(1) Field of the Invention
The invention relates to the manufacture of high density integrated circuits, and more particularly to the manufacture of electrical contacts to such integrated circuits.
(2) Description of the Prior Art
There continues to be a dramatic increase in the package density of integrated circuits. The feature size of these devices has reached one micrometer and is now approaching one half micrometer and below. The size of electrical contact windows are decreased with these decreasing feature sizes. However, the thickness of the dielectric through which these contact windows must pass cannot not be scaled down proportionally. The windows, therefore are now are small in the X-Y direction and large in the Z direction.
The usual technique is to fill these electrical contact windows with tungsten by a chemical vapor deposition method. However, this tungsten technique has many drawbacks from a practical manufacturing point of view. These include the difficulty and cost of the method, and the problems of tungsten contamination of the devices. Other metals have been proposed, but have caused similar problems.
A polysilicon plug for the electrical contact windows either with or without a barrier metal layer has been proposed. It does have the advantage of being easily deposited and adheres well to most materials. M. Kawano et al U.S. Pat. No. 4,833,519; J. L. Klein et al U.S. Pat. No. 4,829,024 and J. Hayden et al "A HIGH-PERFORMANCE SUB-HALF MICRON CMOS TECHNOLOGY FOR FAST SRAMS" Published in IEDM 89 pages 417-420, CH2637-7/89/0000-0417 1989 IEEE describe the use of such polysilicon plugs.
There are problems which must be overcome to make a manufacturable polysilicon plug process. Two major problems involve the conductivity of the polysilicon plug in the electrical contact windows and a successful etchback process. These are related problems to some extent. However, the etchback problem is the most serious in that the polysilicon plug can be partially removed when the polysilicon is etched back to the dielectric. When the dielectric is exposed there is what is termed a microloading effect which causes a greatly accelerated etching of the remaining polysilicon which is within the contact window. Of the three references mentioned in the previous paragraph, only the Klein et al U.S. Pat. No. 4,829,024 mentions and understands this problem. They use alternate layers of doped and undoped polysilicon and the desired endpoint of the etchback is detected by monitoring photoemissions provided from the reaction. A layer of polysilicon is maintained above the dielectric layer. In the above process, a very sophisticated endpoint scheme is required, this fact makes the manufacturing process much less feasible. Further, the use of low temperature deposited amorphous silicon instead of polycrystalline silicon is precluded, since no annealing step after polycrystalline silicon deposition is practiced.